RAM-based Shift Register
Bundled With:
ISE
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Product Details
Documentation
Device Family Support
- Kintex-7
- Virtex-7
- Virtex-6
- Virtex-5
- Virtex-4
- Spartan-6
- Spartan-3A
- Spartan-3A DSP
- Spartan-3E
- Spartan-3
- Artix-7
Requirements
- ISE 13.4 or higher
- ISE IP Update 13.4 or higher
The RAM-based Shift Register IP generates fast, compact FIFO-style registers, delay lines or time-skew buffers using the SRL16/SRL32 mode of the slice LUTs available in Xilinx FPGA devices. Implementing Shift Registers with the SRL16/SRL32 provides large resource and power savings. The IP supports fixed-length or variable-length shift registers.
Key Features
- Supports inputs ranging from 1 to 256 bits wide
- Supports shift register depth from 1 to 1088 for fixed-length or 1 to 1024 for variable-length sift registers.
- Speed or resource optimization for all modes with capability to specify optional output register.
- Instantaneous Resource Estimation
- For use with Xilinx CORE Generator™ and Xilinx System Generator.