Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe)

Product Details

• Ask Xilinx About this Core

Documentation

• Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
• Release Notes (PDF)
• Xilinx End User License Agreement

Device Family Support

• Spartan-6 LXT

Xilinx provides a Spartan-6 FPGA Integrated Endpoint solution for PCI Express® (PCIe) to configure the Spartan-6 FPGA Integrated Endpoint Block for PCIe FPGA and includes additional logic to create a complete Endpoint solution for PCIe. This Xilinx Integrated Endpoint Block Wrapper for PCIe simplifies the design process and reduces time-to-market. Many easy-to-use features and optimal configuration for Endpoint applications are available at no additional cost. This solution can be used in communication, multimedia, server and mobile platforms and enables applications such as imaging, , DVD quality streaming video on the desktop and  Gigabit Ethernet interface cards. This core combined with other Xilinx connectivity solutions helps customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces. All registered ISE users can request a license file by first registering for the wrapper (“Register”)

Key Features

• Compliant with the PCI Express Base Specification 1.1 
• Fully compliant with PCI Express transaction ordering rules
• Supports maximum payload of 512 bytes
• 1 Virtual Channel
• Supported Lane width: x1
• Bandwidth scalability interconnect width
• Pre-implemented optimal buffering for high bandwidth applications 
• LocalLink User Interface for easy bridging to other Xilinx IP
• Uses Spartan-6 FPGA GTP Transceivers
• Design verified by a Xilinx proprietary testbench