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Tri-Mode Ethernet Media Access Controller (TEMAC)

 

Part Number:

EF-DI-TEMAC-SITE

EF-DI-TEMAC-PROJ

AXI Interface Support:

  • AXI4-Lite
  • AXI4-Stream

License:

Core License Agreement

Program:

LogiCORE

Design Tools Support:

  • ISE Design Suite
  • Vivado Design Suite

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Product Details
Documentation
Device Family Support
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 -2L
  • Virtex-7 XT
  • Virtex-6 -1L
  • Virtex-6 HXT
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • Virtex-II Pro
  • Virtex-II
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-3A DSP
  • Spartan-3E
  • Spartan-3

The TEMAC core is ideally suited for the development of high density Gigabit Ethernet communications and storage equipment.

The Xilinx Tri-Mode Ethernet MAC core is a parameterizable core ideally suited for use in networking equipment such as switches and routers. The customizable TEMAC core enables system designers to implement a broad range of integrated Ethernet designs, from low cost 10/100 Ethernet to higher performance 1 Gigabit ports. The TEMAC core is designed to the IEEE 802.3 specification and operates in 1000Mbps, 100 Mbps, and 10 Mbps modes. In addition, it supports both half and full duplex operation. In 1000 Mbps mode, the TEMAC core interfaces with industry standard PHY devices through a GMII/RGMII interface. In 10/100 Mbps mode, the TEMAC uses the MII interface. The Xilinx Tri-Mode Ethernet MAC, combined with the Ethernet 1000BASE-X PCS/PMA or SGMII core, provides a complete and highly flexible solution for the implementation of Ethernet Link and Physical layers. The TEMAC core is delivered through the Xilinx CORE Generator™ tool and is part of the comprehensive suite of Xilinx Ethernet solutions.

Key Features

  • Designed to IEEE 802.3-2005 specification
  • Reconciliation sublayer with GMII/MII or RGMII
  • Configurable half-duplex and full-duplex operation
  • Configured and monitored through an optional independent microprocessor-neutral interface
  • Configurable flow control through MAC Control pause frames; symmetrically or asymmetrically enabled
  • Optional MDIO interface to managed objects in PHY layers (MII Management)
  • Optional clock enables to reduce clock resource usage
  • Support of VLAN frames to specification IEEE 802.3-2005
  • Optional address filter with a selectable number of address table entries
  • Configurable support of jumbo frames of any length
  • Configurable inter-frame gap adjustment
  • Configurable in-band FCS field passing on both transmit and receive paths
  • Ethernet AVB and Ethernet Statistics integrated with TEMAC
 
1.What are the features of the TEMAC core?
2.What interfaces does the TEMAC IP core support?
3.What Xilinx FPGA families and speed grades does the TEMAC core support?
4.Which Xilinx Software version supports this core?
5.What are the target applications for this product?
6.What is the availability, cost and licensing terms for the TEMAC core?
7.Are there any pinout restrictions for the core?
8.Are there any features that can be omitted to reduce the resource utilization of the core?
9.What PHYs is the core compatible with?
10.Is RGMII support available?
11.Has the TEMAC core been verified in hardware?
12.How can I evaluate the core?
13.Where can I find a list of known issues?
14.What other gigabit Ethernet solutions does Xilinx provide?
15.What is the difference between the EF-DI-TEMAC-SITE and EF-DI-TEMAC-PROJ ?

 1. What are the features of the TEMAC core?

The core supports half and/or full-duplex operation, and is designed to the IEEE 802.3-2002 standard specification. Also, TEMAC core supports three different modes, 1 Gbps, 100 Mbps, 10Mbps, of operation. In addition, it provides support for VLAN frames and JUMBO frames of unlimited length. It also provides optional network management features including per packet based statistics vector and flow control. The TEMAC core can be configured and monitored through a processor independent interface, providing users the additional flexibility to pick the ideal processor for their applications.

 2. What interfaces does the TEMAC IP core support?
The new TEMAC core is a parameterized core which may be configured with any one of the following three interfaces:
  • In the Gigabit Mode, TEMAC supports Gigabit Media Independent Interface (GMII) and Reduce Gigabit Media Independent Interface (RGMII). GMII is a byte-wide parallel SDR Interface running at 125 MHz, whereas RGMII is nibble-wide parallel DDR Interface running at 25 MHz to provide 1 Gbps total bandwidth. Also, TEMAC supports MII interface for both 100 and 10 Mbps modes. MII interface is 4-bit wide and runs at 25 MHz in the 100MBps mode. MII interface runs at 2.5MHz in 10 Mbps mode.
 3. What Xilinx FPGA families and speed grades does the TEMAC core support?
GMII Configuration
RGMII Configuration
Virtex-5 (-1)
Virtex-4 (-10)
Virtex-II Pro (-5)
Virtex-II (-4)
Spartan-3 (-4)
Spartan-3E (-4)
Spartan-3A / 3AN/ 3A DSP(-4)
Virtex-5 (-1)
Virtex-4 (-10)
Virtex-II Pro (-5)
Virtex-II (-4)
Spartan-3 (-4)
Spartan-3A / 3AN/ 3A DSP(-4)
 4. Which Xilinx Software version supports this core?
Please see the  data sheet for latest software version supported in this core.
 5. What are the target applications for this product?
The TEMAC core is ideally suited for the development of Gigabit communications and storage equipment. Applications include switches, routers, servers, and networking interface cards on high-performance desktop computing systems. Also, TEMAC in 10/100 mode could be used in consumer applications.
 6. What is the availability, cost and licensing terms for the TEMAC core?

The TEMAC core is available now as part of the Xilinx Ethernet MAC solution . It is sold with a site license, which allows you to access the core and any additional updates which may be made available for a period of one year from your date of purchase.

For pricing information, please contact your distributor or Xilinx FAE.

 7. Are there any pinout restrictions for the TEMAC core?

There are no pinout restrictions for the TEMAC core.

 8. Are there any features that can be omitted to reduce the resource utilization of the core?

Yes. The following features may be omitted when customizing the TEMAC core via the CORE Generator™ :

  • Address filter
  • Management interface

Please refer to the datasheet for complete information on resource utilization.

 9. What PHYs is the core compatible with?

The core has been designed to be compatible with industry standard GE PHYs with GMII interfaces and 10/100 PHYs with MII interface. Please contact your Xilinx FAE for more details on the latest interoperability testing status.

 10. Is RGMII support available?

Yes.

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 11. Has the TEMAC core been verified in hardware?

The Tri-Mode MAC and the client loopback example design delivered with the core have been tested in hardware (ML320 platform) in a Virtex-II Pro. The embedded PowerPC was used to access all configuration and status registers of the core. The GMII/MII of the core was connected to an external BASE-T PHY and the core tested in both full and half duplex modes and at all three speeds. Link Partners used for testing included NIC cards and an Agilent RouterTester 900.

TEMAC has also been verified in ML401 and ML403 Platforms (Virtex-4). Please refer to XAPP443 for more information.

 12. How can I evaluate the core?

To try out the TEMAC customization GUI and generate a gate level Simprim library model which you can use to functionally evaluate the core in your system ("Simulation-only Evaluation"), follow the instructions regarding Xilinx ISE software requirements, Service Pack levels and IP Update installation requirements described on the Evaluation Options link on the TEMAC Product page.

If you additionally wish to perform a Full System Evaluation in hardware, you will also need to request a Full System Evaluation license from the TEMAC evaluation page.

 13. Where can I find a list of known issues?

See the IP Release Notes for known issues, new features and patches

 14. What other Ethernet solutions does Xilinx provide?
The TEMAC core is part of the Xilinx Platform FPGA Connectivity solution, which addresses all aspects of system connectivity in high-performance designs. Xilinx provides the most comprehensive gigabit Ethernet MAC offerings in the programmable industry. In addition to the TEMAC core, Xilinx also provides a 10/100 Ethernet MAC core with OPB or PLB interface for embedded MicroBlaze™ and PowerPC solutions, 1G Ethernet MAC with GMII/RGMII interfaces, 1G PCS layer with 1000-base-x serial/SGMII/TBI interface, 10 GEMAC user-side FIFO design example, a standalone XAUI core, and a 10 Gigabit Ethernet MAC core with a choice of XGMII or XAUI interface.

View a complete listing of Xilinx Ethernet IP solutions for more details.

 15. What is the difference between EF-DI-TEMAC-SITE  and EF-DI-TEMAC-PROJ ?
The site license allows for unlimited number of designs within a 5 mile radius of the purchased site. The single project licenses allows for you to develop one board with multiple FPGA designs using this IP or one FPGA design used on multiple boards.  There is no location restriction for the single project license.  Please contact your local Xilinx sales representative for more details on the two options.  Site and project license agreements can be found at SignOnce Landing page.
 
 
 
 
 
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