Inrevium V-by-One HS IP Core
Part Number:
TIP-VBY1HS
Alliance Program Tier:
Premier
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Device Family Support
- Kintex-7
- Spartan-6
- Spartan-6 LXT
V-by-One® HS standard has been developed by THine Electronics,Inc. to offer capabilities for Flat Panel Display (FPD) markets that are requiring ever-higher frame rates and higher resolutions. Tokyo Electron Device (TED) offers the V-by-One®HS IP Core for Xilinx FPGA that achieves reducing the cable pairs, costs and time to market.This IP includes both Tx and Rx for Xilinx Spartan-6.
Key Features
- Independent Transmitter and Receiver module.
- Protocol compliant with V-by-One® HS standard.
- Supports 1, 2, 4, and 8 lanes operations.
- Uses the GTP transceivers of Spartan-6 LXT families and the GTX transceivers of Virtex-6LXT /SXT families.
Target Markets
- Automotive
- Broadcast
- Consumer
- Industrial Scientific Medical
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| KINTEX-7 Family | XC7K325T | -2 | Vivado 2012.1 | 1496 | 2255 | 14 | 0 | 6 | 4 | 148 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | Feb 12,2013 |
| Company Name | Tokyo Electron Device Ltd. |
| IP Name | Inrevium V-by-One HS IP Core |
| IP Part Number | TIP-VBY1HS |
| Current IP Revision Number | 1.00E |
| Date Current Revision was Released | Apr 11,2010 |
| Release Date of first Version | Apr 11,2010 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 10 |
| Can references be made available? | Y |
| Deliverables | |
| IP Formats available for purchase | Netlist |
| Source Code Formats(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Techbench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | Y |
| FPGA used on board | Spartan-6 |
| Software Drivers Provided? | N |
| Driver OS Support | N/A |
| Implementation | |
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported / version | Xilinx XST / 11.4 |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
| Verfification | |
| Is a documented verification plan available? | No |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators supported | Mentor Questa / 6.5 |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | CVK-PRO (TB-6S-CVK-PRO) |
| Industry standard compliance testing passed | Y |
| Specific compliance test | Connectivity Test from THine |
| Test date | 2010-03-18 17:00:00.0 |
| Are test results available? | N |
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