USB 3.0 Device (USB3_DEV)
Part Number:
USB3_DEV
AXI Interface Support:
- AXI4
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Device Family Support
- Zynq-7000
- Kintex-7
- Virtex-7
- Virtex-6 HXT
- Virtex-6
- Virtex-6 LXT
- Virtex-6 SXT
- Virtex-5
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-5 TXT
- Spartan-6
- Spartan-6 LX
- Spartan-6 LXT
- Spartan-3A
- Spartan-3A DSP
- Spartan-3AN
- Spartan-3E
- Spartan-3
A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of a USB Device interface.
Key Features
- Bulk, control, interrupt and isochronous endpoints and transfers.
- Compact and cost-effective solution.
- Full duplex operation support.
- Integrated DMA engine.
- Power Management support.
- USB 3.0 PIPE & GTX transceiver interface.
- USB 3.0 SuperSpeed support, 5Gbit/s.
- Up to 16 fully configurable endpoints.
Target Markets
- Aerospace & Defense
- Automotive
- Broadcast
- Consumer
- High Performance Computing
- Industrial Scientific Medical
- Wireless Communications
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-7X Family | XC7VX485T | -2 | ISE 14.1, ISE 14.1 | Y | 1632 | 4526 | 12 | 0 | 1 | 1 | 175 |
| KINTEX-7 Family | XC7K325T | -1 | ISE 14.1, ISE 14.1 | Y | 1546 | 4623 | 12 | 0 | 1 | 1 | 170 |
| Zynq-7000 Family | XC7Z045 | -2 | ISE 14.1, ISE 14.1 | Y | 1484 | 4615 | 12 | 0 | 1 | 1 | 175 |
| VIRTEX6LXT Family | XC6VLX75T | -1 | 11.4 | Y | 3779 | 5829 | 13 | 0 | 1 | 1 | 125 |
| VIRTEX5FXT Family | XC5VFX70T | -1 | 11.4 | Y | 5596 | 5596 | 14 | 0 | 1 | 1 | 125 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | Oct 08,2012 |
| Company Name | ASICS World Service, Ltd. |
| IP Name | USB 3.0 Device (USB3_DEV) |
| IP Part Number | USB3_DEV |
| Current IP Revision Number | 1 |
| Date Current Revision was Released | Nov 02,2009 |
| Release Date of first Version | Nov 02,2009 |
| Deliverables | |
| IP Formats available for purchase | Netlist; Source Code |
| Source Code Formats(s) | Other; Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | Y |
| FPGA used on board | Virtex-5 |
| Software Drivers Provided? | Y |
| Driver OS Support | enbedded |
| Implementation | |
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference; Instantiation |
| Custom FPGA Optimization Techniques | GTX |
| Synthesis Software Tools Supported / version | Xilinx XST / 11.4 |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
| Verfification | |
| Is a documented verification plan available? | No |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Code; Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators supported | Cadence NC-Sim / 6.1 |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | HighTech Global Development board |
| Industry standard compliance testing passed | N |
| Specific compliance test | Not Yet |
Products and/or services provided by Alliance Program Members are sold or licensed solely by the Member and not Xilinx. Please be advised that Xilinx hereby disclaims any warranties, express or implied, including warranties of merchantability, fitness for a particular purpose, or noninfringement with respect to any such products and/or services.