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XAUI

 

Bundled With:

ISE

License:

Xilinx End User License

Program:

LogiCORE

Design Tools Support:

  • ISE Design Suite
  • Vivado Design Suite

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Product Details
Documentation
Device Family Support
  • Artix-7
  • Zynq-7000
  • Kintex-7
  • Virtex-7
  • Virtex-6 -1L
  • Virtex-6 HXT
  • Virtex-6 CXT
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-4 FX
  • Virtex-II Pro
  • Spartan-6 LXT

No charge paramaterizable core which utilizes the serial I/O transceivers available in the Virtex®-7, Kintex-7, Artix-7, Zynq-7000, Virtex-6, Virtex-5, Virtex-4 FX, Virtex-II Pro and Spartan®-6 to support the XAUI function.


The Xilinx 10 Gigabit Attachment Unit Interface (XAUI) LogiCORE™ IP provides a 4-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. Operating at an internal clock speed of 156.25 MHz, the core includes the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2008. In addition, the core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2008 clause 45 management registers. The MDIO interface may be omitted to save logic, in which case a simplified management interface is provided via bit vectors.

Key Features

  • Single chip solution for XAUI applications
  • Supports 20G double-rate XAUI (Double XAUI) in 7-Series and Virtex-6 devices using four transceivers at 6.25 Gb/s
  • Designed to IEEE 802.3-2008 specification
  • Allows direct interfacing between Virtex-7, Kintex-7, Artix-7, Zynq-7000, Virtex-6, Virtex-5, Virtex-4 FX, Virtex-II Pro, or Spartan-6 FPGAs and industry standard ASSP PHY devices
  • Supports 32 bit DDR or 64 bit SDR backend interface
  • Uses Digital Clock Management or mixed mode Clock Managers to implement optional XGMII interface clocking
  • Leverages DDR I/O primitives for the optional XGMII interface
  • Uses Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-4, and Spartan-6 transceivers running 4 lanes at 3.125Gbps for the XAUI interface
  • Optional 802.3-2008 clause 48 State Machines
  • Customize using the CORE Generator™ solution
  • Implements DTE XGXS, PHY XGXS and 10G BASE-X PCS in a single netlist
  • Supports 10-Gigabit Fibre Channel (10-GFC) XAUI data rates and traffic
 

The design conforms to the IEEE 802.3ae-2008 standard and includes the following functionality:

  • 8B10B encode/decode with error detection
  • Comma detection
  • RX elastic buffer/channel bonding
  • A state-of-the-art PMA (SERDES)
  • Idle generation on transmit
  • Synchronization state machine on each receive lane
  • Deskew state machine on receive (Channel Bonding)
  • Full set of management registers (per IEEE 802.3ae specifications)

The XAUI core is ideally suited to provide high-performance interconnect technologies for communications equipment and facilitate easy interfacing with 10 Gbps transceivers supporting this standard (XENPAK compliant devices, for example).

XAUI Block Diagram


Related Information

Related Products

 
 
1.What features does the XAUI IP core support?
2.Which Xilinx FPGA families, speed grades and packages does the XAUI core support?
3.Which Xilinx Software version supports this core?
4.What are the target applications for this product?
5.What PHYs is the XAUI core compatible with?
6.What is the availability, cost and licensing terms for the XAUI core?
7.Are there any pinout restrictions for the core?
8.Has the XAUI core been verified in hardware?
9.Are there any features that can be omitted to reduce the resource utilization of the core?
10.What is the impact of these optional features on slice utilization?
11.How can I evaluate the core?
12Where can I find a list of Known Issues?
13.What other Ethernet solutions does Xilinx provide?
                            
 1. What features does the XAUI IP core support?

The XAUI core is delivered through the CORE Generator™ and may be configured by the user with the following options:

  • Support added for ISE®13.1
  • Internal XGMII, for applications where the core communicates with other logic in the same FPGA
  • External XGMII, used when the core is used with logic that is not contained within the same FPGA.
  • IEEE 802.3ae-2008 compliant state machines
  • Optional MDIO interface, or simplified interface with configuration vector

Because the core is parameterized through the CORE Generator, you can tailor the core to your specific feature set requirements.

Latest core changes:

  • Support added for ISE 10.1.3

 

 2. Which Xilinx FPGA families and speed grades does the XAUI core support?

XAUI Device Support
Virtex-7, Kintex-7 (-1, -2, -3)
Artix-7
Zynq-7000
Virtex-6 (-1, -2, -3)
Virtex-6 (20G operation in -3)
Virtex-5 LXT/SXT/FXT (-1, -2, -3)
Virtex-4 FX (-10, -11, -12)** 
Virtex-II Pro (-6, -7)* 
Spartan-6

*XCVP4 or larger devices are required.
** 4V FX20 or larger devices are required

Additionally, the core also must be targeted to a flip-chip package to achieve the required 3.125 Gbps I/O bandwidth for XAUI.

 3. Which Xilinx Software version supports this core?
Please see the data sheet for the latest supported software version.
 4. What are the target applications for this product?
The XAUI core is ideally suited for :
  • Bridging applications - applications requiring the transfer of Ethernet frames across a medium different from Ethernet, where protocol termination is not required (Examples: switch port interfaces).
  • Porting third party 10 Gigabit Ethernet MACs to Virtex-II Pro, Virtex-4 FX, and Virtex-5 MGT XAUI.
  • Interfacing 10 Gigabit Ethernet to other standard interfaces (e.g., SPI-4.2).
  • Backplane applications which require 10 Gbps data rates
  • Chip-to-chip or board-to-board 10G interfaces
 5. What PHYs is the XAUI core compatible with?
The XAUI Core is designed to be compatible with industry standard PHYs which have XAUI interfaces.
 6. What is the availability, cost and licensing terms for the XAUI core?
The XAUI core is provided free of charge and is available now. The parameterizable core is configured through a CORE Generator™ GUI and licensed via the Xilinx LogiCORE ™ Site License. Evaluation and download information can be found on the product page for this core. See the left side bar also for Instructions for Downloading the core.
 7. Are there any pinout restrictions for the core?
The pinouts for the XAUI core are relatively flexible. The main restrictions are those imposed by the target device family selected and are described briefly in the XAUI datasheet. Further details can be found in the Virtex-7/Kintex-7 User Guide, Virtex-6 User Guide, Virtex-5 User Guide, Virtex-4 User Guide, Virtex-II Pro User Guide and RocketIO™ User Guide.

The main pin location considerations for XAUI configuration of the core when targeting Virtex-II Pro are the same for any design which utilizes four channel-bonded MGTs as described in detail in the RocketIO User Guide. Only configurations of the core with all four MGTs placed along a single edge of the device are supported.

 8. Has the XAUI core been verified on hardware?

Virtex-II Pro devices configured with XAUI interfaces have been successfully tested for interoperability at the University of New Hampshire Interoperabilty Lab (UNH IOL) with a number of 10GE equipment vendors and PHYs during three separate XAUI group tests in October 2002, January 2003, and May 2003 on both the Xilinx ML321 and ML330 Virtex-II Pro development boards. (Click here to see the press release regarding the October 2002 group test.)

Contact your local Xilinx FAE for the latest status on hardware verification of the XAUI LogiCORE.

 9. Are there any features that can be omitted to reduce the resource utilization of the core?
The following features may be omitted when customizing the XAUI core via the CORE Generator:
  • MDIO Management interface
  • Tx Elastic Buffer. The Tx Elastic Buffer is used with external XGMII. When the clocking scheme allows, this option may be omitted to save on FPGA resources.
  • IEEE 802.3ae-2002 compliant state machines. Omitting these can save resources if strict 802.3ae compliance is not required for the specific application
  • Full Duplex mode, Tx only simplex mode, Rx only simplex mode
 10. What is the impact of these optional features on slice utilization?
Please refer to the device utilization section of the datasheet.
 11. How can I evaluate the core?
To try out the XAUI LogiCORE customization GUI and generate a gate level Simprim library model which you can use to functionally evaluate the core in your system ("Simulation-only Evaluation"), follow the instructions regarding Xilinx ISE software, Service Pack levels and IP Update installation requirements described here.
 12. Where can I find a list of Known Issues?

See the IP Release Notes for known issues, new features and patches

 13. What other Ethernet solutions does Xilinx provide?

The XAUI core is part of the Xilinx Platform FPGA SystemIO solution, which addresses all aspects of system connectivity in high-performance designs. Xilinx provides the most comprehensive Ethernet MAC offerings in the programmable industry. In addition to the XAUI core, Xilinx also provides an Ethernet 1000BASE-X Adapter core for 1 Gbps applications.

Additionally, Xilinx also offers these Ethernet solutions:

  • a 10 Gb Ethernet MAC core with XGMII interface
  • a RXAUI interface
  • a Tri-mode Ethernet MAC with GMII interface
  • a 1 Gb Ethernet MAC core with a choice of GMII interface or RGMII interface, plus a configuration with a Processor Local Bus (PLB) interface
  • a standalone 1000BASE-X PCS/PMA core with choice of TBI, or 1000BASE-X PMA or SGMII interface

A complete listing of Xilinx Ethernet IP solutions .

 
 
 
 
 
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