UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Accumulator

Product Description

The Accumulator IP provides LUT and single DSP48 slice accumulation implementations. The Accumulator module can implement adder-based, subtracter-based, and dynamically configurable adder/subtracter-based accumulators operating on signed or unsigned data. The Accumulator module can generate adder-based, subtracter-based and adder/subtracter-based accumulators operating on signed or unsigned data. The function can be implemented in a single DSP48 slice or LUTs (but currently not a hybrid of both). Pipelining is available for both implementations.


Key Features and Benefits

  • Supports fabric implementation inputs ranging from 2 to 256 bits wide
  • Supports DSP48 slice implementation with inputs ranging from 2 to 36 or 48 bits wide (varies with device family selection).
  • Optional carry output.
  • Latency configuration of manual or automatic for maximal speed performance.
  • Instantaneous Resource Estimation

Resource Utilization


Support

Featured Documents

Default Default Title Document Type Date
Page Bookmarked