The AHB-Lite (Advanced High Performance Bus) to AXI bridge translates AHB-Lite transactions into AXI4 transactions. It functions as an AHB-Lite slave on the AHB bus and as an AXI master on the AXI bus.
Key Features
- AHB-Lite interface based on the AHB specification
- Supports 1:1 (AXI:AHB) synchronous clock ratio
- AHB and AXI data widths are same and either 32 or 64 bit based on the configuration
- Supports narrow transfers on the AHB interface
- Supports burst termination on the AHB during which dummy transfers are initiated on the AXI interface
- Timeout feature to indicate no response from AXI slave during write response and read data phases