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Aurora 64B/66B

Product Description

Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA

Aurora is a LogiCORE™ IP designed to enable easy implementation of Xilinx transceivers while providing a light-weight user interface on top of which designers can build a serial link. Aurora 64B/66B is a scalable, lightweight, link-layer protocol for high-speed serial communication. The protocol specification is open and available upon request. The IP is free to use from the IP Catalog on Xilinx silicon devices.

Aurora is typically used in applications requiring low-cost, high data-rate, scalable and flexible means to build a serial data channel. Its simple framing structure can easily be used to encapsulate data from existing protocols, and its electrical requirements are compatible with commodity equipment. Aurora can be used to provide increased performance without high FPGA resource costs, software redevelopment, or exotic physical infrastructure.

Applications
Aurora 64B/66B can be used in any application that requires serial point-to-point connectivity. Example applications include:

  • Chip-to-chip links. Significantly reduce the trace count on PCBs with minimal FPGA resource costs. Examples: Line cards, multi-device partitioning, high-speed ASIC-FPGA connections
  • Board-to-board and backplane links. Increase system throughput using existing cables, connectors, and backplanes. Examples: Short-reach optics, ATCA Backplanes.
  • Streaming data applications. Infinite frames with arbitrary Idle insertion make it easy to stream data through Aurora channels. Examples: Data cell transfer with low overhead, Video streams.
  • One-way connections. Aurora simplex channels enable low cost, high-speed serial links in a single direction. Examples: Video data offload, long-haul data transfer.

Key Features & Benefits

  • Enhanced with a line rate up to 25.7813 Gb/s for GTY transceivers
  • General-purpose data channels with throughput range from 500 Mb/s to over 400 Gb/s
  • Supports up to 16 consecutively bonded 7 series GTX/GTH, UltraScale™ GTH/GTY or UltraScale+™ GTH/GTY transceivers
  • Aurora 64B/66B protocol specification v1.3 compliant (64B/66B encoding)
  • Low resource cost with very low (3%) transmission overhead
  • Easy-to-use AXI4-Stream based framing and flow control interfaces
  • Automatically initializes and maintains the channel
  • Full-duplex or simplex operation
  • 32-bit Cyclic Redundancy Check (CRC) for user data
  • Added support for the Simplex Auto Link Recovery feature
  • Supports RX polarity inversion
  • Big endian/little endian AXI4-Stream user interface
  • Fully compliant AXI4-Lite DRP interface
  • Configurable DRP, INIT clock
  • Delivered as source code
  • Single/Differential clocking option for GTREFCLK and core INIT_CLK
xilinx-131x43
Get License
  • Bundled With: Vivado Design Suite
    ISE Design Suite
  • License: Xilinx End User License Agreement

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