Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA.
Aurora is a LogiCORE IP designed to enable easy implementation of Xilinx transceivers while providing a light-weight user interface on top of which designers can build a serial link. Aurora 8B/10B is a scalable, lightweight, link-layer protocol for high-speed serial communication. The protocol specification is open and available upon request. The IP is free from the IP Catalog on Xilinx silicon devices.
Aurora is typically used in applications where other industry standard serial interfaces are not needed and Aurora delivers low-cost, high data-rate, scalable and flexible means to build a serial data channel. Its simple framing structure can easily be used to encapsulate data from existing protocols, and its electrical requirements are compatible with commodity equipment. Aurora can be used to provide increased performance without high FPGA resource costs, software redevelopment, or exotic physical infrastructure.
Aurora can be used in any application that requires serial point-to-point connectivity. Example applications include:
- Chip-to-chip links. Significantly reduce the trace count on PCBs with minimal FPGA resource costs. Examples: Line cards, multi-device partitioning, high-speed ASIC-FPGA connections
- Board-to-board and backplane links. Increase system throughput using existing cables, connectors, and backplanes. Examples: Short-reach optics, ATCA Backplanes
- Streaming data applications. Infinite frames with arbitrary Idle insertion make it easy to stream data through Aurora channels. Examples: Data cell transfer with low overhead, Video streams
- One-way connections. Aurora simplex channels enable low cost, high-speed serial links in a single direction. Examples: Video data offload, long-haul data transfer
Key Features and Benefits
- General-purpose data channels with throughput range from 480 Mb/s to 84.48 Gb/s
- Supports up to 16 consecutively bonded 7 series GTX/GTH, UltraScale™ GTH or UltraScale+™ GTH transceivers and 4 bonded GTP transceivers
- Aurora 8B/10B protocol specification v2.3 compliant
- Low resource cost (see Resource Utilization)
- Easy-to-use AXI4-Stream based framing (or streaming) and flow control interfaces
- Automatically initializes and maintains the channel
- Full-duplex or simplex operation
- 16-bit additive scrambler/descrambler
- 16-bit or 32-bit Cyclic Redundancy Check (CRC) for user data
- Delivered as source code
- Automatic Hot-Plug detection & recovery support
- Configurable DRP/INIT clock
- Single/Differential clocking option for GTREFCLK and core INIT_CLK