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AXI AMM Bridge

Product Description

The Xilinx® LogiCORE™ AXI AMM Bridge IP core connects Avalon bridge slave IPs with AXI interface masters. It translates AXI4-Lite and AXI4 interface transactions into Avalon bridge transactions. This IP allows parameter configuration to match Avalon bridge slave interface properties and enables seamless interface with the AXI interface system.

Key Features & Benefits

  • Supports configurable AXI4-Lite and AXI4 interface
  • Supports 32-bit data width for AXI4-Lite interface
  • Supports up to 1,024-bit data width for memory mapped AXI interfaces
  • Support for Fixed and Variable Wait
  • Support for Fixed Variable Latency
  • AXI response generation if no response signal from Avalon slave
  • Data phase timeout logic
  • Byte and Word addressing
xilinx-131x43
  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement

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