AXI Chip2Chip
AXI Interface Support:
- AXI4
- AXI4-Lite
Bundled With:
Vivado, ISE and EDK
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
- IDS Embedded Edition
Included at no additional charge with EDK software.
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Documentation
Device Family Support
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-7 XT
The LogiCORE™ IP AXI Chip2Chip is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The adaptable block provides bridging between AXI systems for Multi-FPGA System on Chip solutions. The core supports multiple FPGA-to-FPGA interfacing options and provides a low pin count, high performance AXI chip-to-chip bridging solution.
Key Features
- Supports AXI4 Memory Mapped user interface
- Supports optional AXI4-Lite data width of 32 bits
- Supports Single Ended or differential SelectIO™ FPGA interface
- Independent Master or Slave mode selection for AXI4 and AXI4-Lite interfaces
- Supports 32-to-64 bit AXI data width
- Supports asynchronous active-Low reset
- Supports Common Clock or Independent Clock operations
- Supports multiple Width Conversion options for reduced I/O utilization
- Supports Link Detect FSM with deskew operation
- Differential I/O support (Differential Clock Or Differential Clock and data option)
- Allows all five AXI channels to operate independently
- Supports an additional high-priority cut through channel for communicating interrupts
- Provides a dedicated high-priority internal channel for link status monitoring and reporting
- Generates Link Error and Multi-Bit Error Error interrupts