We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AXI Chip2Chip

Product Description

Included at no additional charge with EDK software.

The LogiCORE™ IP AXI Chip2Chip is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The adaptable block provides bridging between AXI systems for Multi-FPGA System on Chip solutions.  The core supports multiple FPGA-to-FPGA interfacing options and provides a low pin count, high performance AXI chip-to-chip bridging solution.

Key Features & Benefits

  • Supports AXI4 Memory Mapped user interface
  • Supports optional AXI4-Lite data width of 32 bits
  • Supports Single Ended or Differential SelectIO™ FPGA interface and Aurora FPGA interface
  • Independent Master or Slave mode selection for AXI4 and AXI4-Lite interfaces
  • Supports 32-to-64 bit AXI data width
  • Supports asynchronous active-Low reset
  • Supports Common Clock or Independent Clock operations
  • Supports multiple Width Conversion options for reduced I/O utilization
  • Supports Link Detect FSM with deskew operation
  • Differential I/O support (Differential Clock Or Differential Clock and data option)
  • Allows all five AXI channels to operate independently
  • Supports an additional high-priority cut through channel for communicating interrupts
  • Provides a dedicated high-priority internal channel for link status monitoring and reporting
  • Generates Link Error and Multi-Bit Error Error interrupts
  • Supports ECC with single-bit error correction for Aurora interface
  • Bundled With: Vivado Design Suite
    Embedded Development Kit
    ISE Design Suite
  • License: Xilinx End User License Agreement

Featured Documents

Page Bookmarked