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AXI Verification IP (VIP)

Product Description

The AXI VIP can be used to verify connectivity and basic functionality of AXI masters and AXI slaves with the custom RTL design flow. It also supports Passthrough mode which transparently allows the user to monitor transaction information/throughput or drive active stimulus. The AXI VIP provides example test benches and tests that demonstrate the abilities of AXI3, AXI4, and AXI4-Lite. These examples can be used as a starting point to create tests for custom RTL design with AXI3, AXI4, and AXI4-Lite interface. The examples can be accessed from IP Integrator.

There are no licenses required for use of AXI Verification IP.

Key Features & Benefits

  • Supports all protocol data widths and address widths, transfer types and responses
  • Full AXI Protocol Checker support
  • Integrated ARM Licensed Protocol Assertions
  • Transaction level protocol checking (burst type, length, size, lock type, cache type)
  • Behavioral SystemVerilog Syntax
  • SystemVerilog class-based API
  • Configurable simulation messaging
  • Delivered in Vivado Design Suite
  • SystemVerilog example designs and test benches delivered in IP Integrator
  • Supported Simulators: Aldec Riviera-PRO, Cadence Incisive Enterprise Simulator, Vivado Simulator, Mentor Graphics Questa Prime and Synopsys VCS

Featured Documents

  • License: Xilinx End User License Agreement

In addition to the AXI VIP, the Zynq®-7000  simulation model that uses the AXI VIP is now for available in Vivado 2017.1.  It is accessible through the Processor Configuration Wizard of the Zynq-7000 processor system in the IP Catalog.

The Zynq Ultrascale+ MPSoC™ simulation model that uses the AXI VIP is planned for availability in Vivado 2017.3

Featured Documents

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