AXI4-Stream Interconnect

Documentation

• Release Notes (PDF)
• Xilinx End User License Agreement
• AXI Stream Interconnect

Device Family Support

• Zynq-7000
• Artix-7
• Kintex-7
• Virtex-7
• Virtex-6
• Spartan-6

Xilinx provides the AXI4-Stream Interconnect core which provides capability to connect multiple master/slave AMBA® AXI4-Stream protocol compliant endpoint IP.

The AXI4-Stream Interconnect is a key Interconnect Infrastructure IP which enables connection of heterogeneous master/slave AMBA® AXI4-Stream protocol compliant endpoint IP. The AXI4-Stream Interconnect routes connection from one or more AXI4-Stream master channels to one or more AXI4-Stream slave channels. 

Key Features

• Configurable multiple master to multiple slave (up to 16x16) capable cross-point switch.  
• Arbitrary TDATA byte width conversion.
• Synchronous and asynchronous clock rate conversion.
• Configurable data-path FIFO buffers including store and forward (packet) capable FIFOs.
• Optional register slice at boundaries to ease timing closure.   
• Support for multiple clock domains.