AXI4-Stream to Video Out
AXI Interface Support:
- AXI4-Stream
Bundled With:
ISE
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- ISE Design Suite
- Vivado Design Suite
Included at no additional charge with ISE software.
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Product Details
Documentation
Device Family Support
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6 HXT
- Virtex-6 LXT
- Virtex-6 SXT
- Spartan-6 LX
- Spartan-6 LXT
- Zynq-7000
Xilinx AXI4-Stream to Video Out IP core enables video designers to quickly and easily connect video processing blocks that use AXI4-Stream to external video sinks.
The AXI-4 Stream to Video Out LogiCORE™ IP core converts AXI4-Stream interface signals to a standard parallel video output interface with timing signals. The AXI4-Stream interface accepts signals that are compliant to the AXI4-Stream Video Protocol as defined in the AXI Reference Guide (UG761), and as is implemented on most Xilinx Video IP cores. The output interface is suitable for use with many external video sinks and contains standard video timing signals including Vsync, Hsync, Vblank, Hblank, DE and pixel clock. This enables video designers to quickly and easily connect video processing blocks with an AXI4-Stream interface to an external video sink such as a DVI PHY. This core works in conjunction with the Xilinx Video Timing Controller (VTC) core to generate the video format timing signals. Source code is provided with the core to allow customers to adapt the core to work with unique video signals that may not already be included in the core.Key Features
- AXI4-Stream interface is compliant with the AXI4-Stream Video Protocol as described in the AXI Reference Guide (UG761)
- Parallel Video data output includes common video timing signals such as Vsync, Hsync, Vblank, Hblank and active video
- Configurable output data width of 8-64 bits enables use with a variety of video data formats such as DVI, monochrome data, etc.
- Supports 1080P60 pixel clock rates in all supported devices families
- Supports 4kx2k at 24Hz clock rates in supported high performance devices
- Designed to operate in conjunction with the Xilinx Video Timing Controller IP Core
- Handles asynchronous clock boundary crossing between AXI4-Stream clock domain and video clock domain
Related Information
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| 1. What deliverables are provided with the AXI4-Stream to Video Out Core core? | ||
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| 2. What are the target applications for this product? | ||
Video and image processing applications in Aerospace and Defense, Automotive, Broadcast, Consumer, Industrial and Medical applications. | ||
| 3. What Xilinx FPGA families and speed grades does the AXI4-Stream to Video Out Core support? | ||
Please refer to the System Requirements Schedule for information on supported FPGA device families and speed grades. | ||
| 4. What is the availability, cost and licensing terms for the AXI4-Stream to Video Out Core ? | ||
The AXI4-Stream to Video Out Core is available now. The core is included with Xilinx ISE software and entitles you to Xilinx world class technical support and access to any future update. Source code is included with the core to enable customers to modify the core to support other video signal configurations that may not be already included with the core. This core is provided under the terms of the Xilinx LogiCORE End User License Agreement. | ||
| 5. What are the FPGA resource requirements for the core, and are there any features that can be omitted to reduce this? | ||
Refer to the data sheet for detailed resource requirements. Resource requirements are dependent upon the option selected at synthesis time. | ||
| 6. Has the AXI4-Stream to Video Out core been verified in hardware? | ||
Yes | ||
| 7. How can I evaluate the core | ||
The AXI4-Stream to Video Core is included with ISE. No evaluation licensing is required. | ||
| 8. Where can I find a list of Known Issues? | ||
Xilinx IP Release Notes: xtp205 contains a complete listing of the current known issues for the core. |