AXI to APB Bridge
AXI Interface Support:
- AXI4-Lite
Bundled With:
Both EDK and Vivado
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- IDS Embedded Edition
Documentation
Device Family Support
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6 HXT
- Virtex-6 LXT
- Virtex-6 SXT
- Spartan-6 LX
- Spartan-6 LXT
The AXI (Advanced eXtensible Interface) to APB (Advanced Peripheral Bus) Bridge translates AXI4-Lite transactions into APB transactions. It functions as a slave on the AXI4-Lite interface and as a master on the APB interface. The AXI to APB Bridge main use model is to connect the APB slaves with AXI masters.
Key Features
- AXI interface is based on the AXI4-Lite specification
- APB interface is based on the APB3 specification, supports optional APB4 selection
- Supports 1:1 (AXI:APB) synchronous clock ratio
- Connects as a 32-bit slave on 32-bit AXI4-Lite
- Connects as a 32-bit master on 32-bit APB3/APB4
- Supports up to 16 APB slaves
- Supports optional data phase time out