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AXI to APB Bridge

Product Description

The AXI (Advanced eXtensible Interface) to APB (Advanced Peripheral Bus) Bridge translates AXI4-Lite transactions into APB transactions. It functions as a slave on the AXI4-Lite interface and as a master on the APB interface. The AXI to APB Bridge main use model is to connect the APB slaves with AXI masters.

Key Features & Benefits

  • AXI interface is based on the AXI4-Lite specification
  • APB interface is based on the APB3 specification, supports optional APB4 selection
  • Supports 1:1 (AXI:APB) synchronous clock ratio
  • Connects as a 32-bit slave on 32-bit AXI4-Lite
  • Connects as a 32-bit master on 32-bit APB3/APB4
  • Supports up to 16 APB slaves
  • Supports optional data phase time out
xilinx-131x43
  • Bundled With: Vivado Design Suite
    Embedded Development Kit
  • License: Xilinx End User License Agreement

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