AXI Central DMA Controller
AXI Interface Support:
- AXI4
- AXI4-Lite
Bundled With:
EDK
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Documentation
Device Family Support
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6 HXT
- Virtex-6 LXT
- Virtex-6 SXT
- Spartan-6 LX
- Spartan-6 LXT
The AXI Central Direct Memory Access (AXI CDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI CDMA engine provides high-bandwidth direct memory access between memory and AXI Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface, suitable for the Xilinx MicroBlaze™ microprocessor.
Key Features
- AXI4 Compliant
- Primary AXI Memory Map data width support of 32, 64, 128, and 256 bits
- Primary AXI Stream data width support of 8, 16, 32, 64, 128, and 256 bits
- Optional Data Re-Alignment Engine
- Optional Gen-Lock Synchronization
- Independent, asynchronous channel operation