AXI DMA Controller
AXI Interface Support:
- AXI4
- AXI4-Lite
- AXI4-Stream
Bundled With:
EDK
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- IDS Embedded Edition
Included with Xilinx ISE™ Software. AXI DMA v5.00.a Available Now
Documentation
Device Family Support
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6
- Virtex-5
- Virtex-4
- Spartan-6
Requirements
- ISE 13.3 or higher
- ISE IP Update 13.3 or higher
The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between memory and AXI4-Stream-type target peripherals. Its optional scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface.
Key Features
- AXI4 and AXI4-Stream compliant
- Optional Scatter/Gather (SG) DMA support. When Scatter/gather mode is not selected the IP operates in Simple DMA mode.
- Primary AXI4 Memory Map and AXI4-Stream data width support of 32, 64, 128, 256, 512, and 1024 bits
- Optional Data Re-Alignment Engine
- Optional AXI Control and Status Streams
- For use with Xilinx CORE Generator™ and Xilinx Embedded Development Kit (EDK)