AXI External Peripheral Controller

Documentation

• AXI External Peripheral Controller
• Xilinx End User License Agreement

Device Family Support

• Zynq-7000
• Artix-7
• Kintex-7
• Virtex-7
• Virtex-6
• Spartan-6

The AXI External Peripheral Controller (AXI EPC IP Core) supports data transfers between the AXI4 Interface and external synchronous and/or asynchronous peripheral dices evices such as USB and LAN devices, which have processor interface. Examples of peripheral devsupported by the AXI EPC include the 10/100 non-PCI Ethernet single chip (SMSC LAN91C111) from SMSC and CY7C67300 USB Controller from Cypress Semiconductor devices.

Key Features

• Connects as a 32-bit slave on AXI4-Lite Interface
• Byte enable support
• Parameterized support of up to four external peripheral devices with each device configured with separate base address and high address range
• Supports both synchronous and asynchronous access modes of peripheral devices with the support for a separate clock domain for synchronous peripheral devices
• Supports both multiplexed and non-multiplexed address and data buses
• The data width of peripheral devices is independently configured to 8-bit, 16-bit or 32-bit with the provision to enable data width matching when the AXI data width is greater than that of peripheral device
• Configurable timing parameters for peripheral bus interface
• Tested with the SMSC LAN91C111 and the Cypress CY7C67300 USB Controller devices