EF-DI-TEMAC (for soft configurations)
EDK
Xilinx End User License
LogiCORE
This core provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers). The transmit and receive data interface is via the AXI4-Stream interface. This core has been designed incorporating the applicable features described in IEEE Std. 802.3-2003.