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AXI 1G/2.5G Ethernet Subsystem

Product Description

The AXI Ethernet Subsystem provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers). The transmit and receive data interface is via the AXI4-Stream interface. This core has been designed incorporating the applicable features described in IEEE Std. 802.3-2012.

Key Features & Benefits

  • 10/100/1000 Mbps support
  • 2500 Mbps non-processor mode support
  • 1588 1-step and 2-step support for UltraScale and 7 series GTX and GTH
  • Independent 2K, 4K, 8K, 16K, or 32K Byte TX and RX
  • Filtering of "bad" receive frames
  • Support for several PHY interfaces
  • Media Independent Interface Management access to PHY
  • Full Duplex and Half-Duplex support
  • Optional support for jumbo frames up to 9K Bytes
  • Support for VLAN frames
xilinx-131x43
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  • Part Number: EF-DI-TEMAC-PROJ
    EF-DI-TEMAC-SITE (for soft configurations)
  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement

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