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AXI Interrupt Controller

Product Description

The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers used for checking, enabling, and acknowledging interrupts are accessed through a slave interface for the AMBA® protocol’s AXI (Advanced Micro controller Bus Architecture Advanced eXtensible Interface) specification. The number of interrupts and other aspects can be tailored to the target system. This AXI INTC core is designed to interface with the AXI4-Lite protocol.

Key Features & Benefits

  • AXI interface is based on the AXI4-Lite specification
  • Configurable number of (up to 32) interrupt inputs
  • Single interrupt output
  • Supports relocatable base address in MicroBlaze
  • Easily cascaded to provide additional interrupt inputs
  • Priority between interrupt requests is determined by vector position. The least significant bit (LSB, in this case bit 0) has the highest priority
  • Interrupt Enable Register for selectively enabling individual interrupt inputs
  • Master Enable Register for enabling interrupt request output
  • Supports Fast Interrupt mode
  • Support for nested interrupts
  • Configurable Software Interrupt capability
xilinx-131x43
  • Bundled With: Vivado Design Suite
    Embedded Development Kit
  • License: Xilinx End User License Agreement
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