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AXI4-Lite IP Interface (IPIF)

Product Description

The LogiCORE™ IP AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of ARM® AMBA® AXI control interface compatible products. It provides a point-to-point bidirectional interface between a user IP core and the Xilinx LogiCORE IP AXI Interconnect core. This version of the AXI4-Lite IPIF has been optimized for slave operation on the AXI interface. It does not provide support for Direct Memory Access (DMA) and IP Master Services.

Key Features & Benefits

  • Supports 32-bit slave configuration
  • Supports read and write data transfers of 32-bit width
  • Supports multiple address ranges
  • Read has higher priority over write
  • Reads from holes in the address space return 0x00000000
  • Writes to holes in the address space after the register map are ignored and receive an OKAY response
  • Both AXI and IP Interconnect (IPIC) are little endian
  • Provides word-aligned addresses at the IPIC interface

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

xilinx-131x43
  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement

Featured Documents

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