AXI PCI Express (PCIe)
AXI Interface Support:
- AXI4
Bundled With:
EDK
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
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Documentation
Device Family Support
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6
- Spartan-6
- Zynq-7000
The AXI PCIe IP is designed for the Xilinx Embedded Development Kit (EDK) and Xilinx Platform Studio (XPS) tool flow. The AXI PCIe IP provides an interface between an AXI4 customer user interface and PCI Express (PCIe®) using the Xilinx Integrated Block for PCI Express (PCIe). The AXI PCIe IP provides a full transaction level translation of AXI4 commands to PCIe TLP packets and PCIe requests to AXI4 commands.
Key Features
- Support AXI4 memory access to PCIe memory
- Provide AXI4 master access for PCIe devices
- Translate AXI4 transactions to appropriate PCIe Transaction Layer Packets (TLP) packets
- Track and Manage PCIe TLPs that require completion processing
- Indicate error conditions detected by the PCIe core through interrupt