The AXI PCIe® Gen 3 Subsystem core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core. The AXI4 PCIe sub-system provides full bridge functionality between the AXI4 architecture and the PCIe network. The sub-system is composed of the PCIe core, the GT interface and the AXI4 interface. The bridge circuit is implemented in the FPGA fabric and the PCIe core and GT are hard-core elements in the FPGA.
The AXI4 PCIe core provides a transaction level translation of AXI4 commands to PCIe TLP packets and PCIe requests to AXI4 commands.
Key Features and Benefits
- AXI Bridge for PCIe Gen3 supports UltraScale architecture and Virtex-7 XT
- DMA/Bridge Subsystem for PCI Express in AXI Bridge mode supports UltraScale+ Integrated Blocks for PCI Express
- Maximum Payload Size (MPS) up to 256 Bytes
- Multiple Vector Messaged Signaled Interrupts (MSIs)
- Memory mapped AXI4 access to PCIe space
- DMA/Bridge Subsystem for PCIe in AXI Bridge mode supports Maximum Payload Size (MPS) up to 1024 bytes
- MSI-X interrupt support
- Legacy interrupt support
- Optimal AXI4 pipeline support for enhanced performance
- PCIe access to memory mapped AXI4 space
- Tracks and manages TLP completion processing