AXI Quad SPI

Documentation

• AXI Quad SPI
• Xilinx End User License Agreement

Device Family Support

• Zynq-7000
• Artix-7
• Kintex-7
• Virtex-7
• Virtex-6
• Spartan-6

The AXI Quad Serial Peripheral Interface connects the AXI4 interface to those SPI slave devices which are supporting the Dual or Quad SPI protocol along with Standard SPI protocol instruction set. As an example, this core provides a serial interface to SPI slave devices such as SPI serial flash from Winbond/Numonyx which support Dual and Quad SPI protocol along with Standard SPI interface. The Dual/Quad SPI is the enhancement to the Standard SPI protocol that delivers a simple method for a master and a selected slave to exchange data.

Key Features

• Connects as a 32-bit AXI4-Lite slave
• Supports configurable SPI modes - Standard SPI Mode, Dual SPI Mode or Quad SPI Mode
• Supports slave select (SS) bit for each slave on the SPI bus
• Supports programmable clock phase and polarity
• Supports continuous transfer mode for automatic scanning of a peripheral
• Supports configurable FIFO depth (16 or 256 element deep in Dual/Quad/Standard SPI mode)