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AXI Slave Burst

Product Description

The LogiCORE® IP AXI Slave Burst is an interface between the AXI4 memory-mapped interface to the IPIC (IP Inter Connect). This core is designed to provide a smooth migration path to the burst-supported IP from PLBv46 to AXI4 with minor updates in the interface. The core provides a point to point bi-directional interface between a user IP core and the AXI4 interconnect. This core acts as master on IPIC while it behaves as a slave on AXI4.

Key Features & Benefits

  • AXI4 Interface: 32 Bit Address bus, 32/64/128 Bit configurable data bus
  • IPIC Interface: 32 Bit Address bus, 32/64/128 Bit configurable data bus
  • Supports 1:1 (AXI4:IPIC) synchronous clock
  • Supports 1:1 (AXI4:IPIC) data width
  • AXI4 Interface
  • IPIC Interface
xilinx-131x43
  • Bundled With: Vivado Design Suite
    Embedded Development Kit
  • License: Xilinx End User License Agreement
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