Xilinx provides AXI Traffic Generator IP which as AXI4 Master can generate AXI4 traffic (AXI4 and AXI4-Stream) for various modules/interconnect connected in system
The Xilinx LogiCORE™ IP Advanced eXtensible Interface (AXI) Traffic Generator is a core that stresses the AXI4 and AXI4-Stream interconnect and other AXI4 peripherals in the system. It generates a wide variety of AXI4 transactions based on the core programming
Key Features
- AXI4 interface for register access and data transfers
- Supports multi-mode operation (AXI4-Master, AXI4-Slave, AXI4-Stream Master)
- Flexible data width capability (32/64-bit) on Slave and (32/64/128/256/512-bit) on Master AXI4 interface
- Interrupt pin indicating core completed generation of traffic
- Error interrupt pin indicating error occurred during core operation. Error registers can be read to understand the error occurred