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LogiCore AXI Traffic Generator

Product Description

Included at no additional charge with Vivado Design and System edition of software.

Xilinx provides AXI Traffic Generator IP which as AXI4 Master can generate AXI4 traffic (AXI4 and AXI4-Stream) for various modules/interconnect connected in system

The Xilinx LogiCORE™ IP Advanced eXtensible Interface (AXI) Traffic Generator is a core that stresses the AXI4 and AXI4-Stream interconnect and other AXI4 peripherals in the system. It generates a wide variety of AXI4 transactions based on the core programming

Key Features & Benefits

  • AXI4 interface for register access and data transfers
  • Supports multi-mode operation (AXI4-Master, AXI4-Slave, AXI4-Stream Master)
  • Flexible data width capability (32/64-bit) on Slave, (32/64/128/256/512-bit) on Master AXI4 interface and (8/16/32/64/128/256/512/1,024-bit) on Master AXI4-Stream interface
  • Supports AXI4-Lite Master interface for system initialization in processor-less system
  • Interrupt pin indicating core completed generation of traffic
  • Error interrupt pin indicating error occurred during core operation. Error registers can be read to understand the error occurred
  • Initialization support to internal RAM (CMDRAM, PARAMRAM, and MSTRAM) allows user to initialize the contents of all RAMs for a desired traffic profile
  • External global start/stop to synchronize all AXI Traffic Generators in system and to enable AXI Traffic Generator without processor intervention
  • Supports High level traffic generation for different traffic profiles such as Ethernet, Video, PCIe
  • Supports infinite looping over its read and write queues to generate traffic for long running test cases (e.g. when running in parallel with SW)
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  • License: Xilinx End User License Agreement

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