AXI XADC Core

Documentation

• AXI XADC
• 7 Series FPGAs XADC (PDF)
• Release Notes (PDF)
• Xilinx End User License Agreement

Device Family Support

• Zynq-7000
• Artix-7
• Kintex-7
• Virtex-7
• Virtex-7 XT

AXI XADC IP provides the controller interface for System Monitor XADC hard macro on the Virtex®-7, Kintex™-7, Artix™-7 FPGA families and Zynq-7000 devices. This IP is a 32-bit slave peripheral with an AXI4-Lite interface which provides the controller interface for the XADC hard macro on the Virtex-7, Kintex-7, Artix-7 FPGA families and Zynq-7000 devices. It supports on-chip monitoring of supply voltages and temperature. This IP supports one dedicated high bandwidth differential analog-input pair and 16 auxiliary low bandwidth differential analog-input pairs.

Key Features

• Connects as a 32-bit AXI4-Lite slave
• Supports two 12-bit, 1 Mega-Samples Per Second (MSPS) Analog-to-Digital Converters (ADC)
• Supports on-chip monitoring of supply voltages and temperature
• Supports simultaneous sequencer mode when both the ADC’s are in use
• Supports one dedicated high bandwidth differential analog-input pair and 16 auxiliary low bandwidth differential analog-input pairs
• Supports automatic alarms based on user defined limits
• Supports optional interrupt request generation