ChipScope AXI Monitor

AXI Interface Support:

AXI4-Stream
AXI4
AXI4-Lite

Bundled With:

Both ISE and EDK

License:

Xilinx End User License

Program:

LogiCORE

Design Tools Support:

ISE Design Suite
IDS Embedded Edition

Product Information
Resources

Documentation

Device Family Support

Zynq-7000
Kintex-7
Virtex-7
Virtex-6
Spartan-6

The ChipScope™ AXI Monitor core is designed to monitor and debug AXI interfaces. The core allows the probing of any signals going from a peripheral to the AXI interconnect. For example, the user can instantiate a monitor on a MicroBlaze™ instruction or data interface to observe all memory transactions going in and out of the processor.

Key Features

Selectable data samples
Generic Trigger/Data Unit with selectable width
Auto-generated CDC file
Multiple monitor support in single system through the use of trigger in and trigger out ports
Allows multiple match units per trigger group
Added functionality for more than one match unit per trigger group
Adjustable counter size for triggers
Selectable AXI Protocol Check monitoring for the AXI4 Memory Map and AXI4-Lite interface
Supports connection to AXI3 Protocol Cores
Supports EDK and standard CORE Generator flows