ChipScope Pro IBERT for 7 Series GTP
Bundled With:
Both ISE and Vivado
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- ISE Design Suite
Documentation
Device Family Support
- Artix-7
The customizable LogiCORE™ IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTP transceivers is designed for evaluating and monitoring the GTP transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTP transceivers. Communication logic is also included to allow the design to be run-time accessible through JTAG. This core can be used as a self-contained or open design, based on customer configuration, and as described in this document.
Key Features
- Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core
- Provides a user-selectable number of 7 series FPGA GTP transceivers
- Transceivers can be customized for the desired line rate, reference clock rate, reference clock source, and datapath width
- Requires a system clock that can be sourced from a pin or one of the enabled GTP transceivers
Related Information
Related Products
- ChipScope Integrated Controller (ICON)
- ChipScope PRO Virtual Input/Output (VIO)
- ChipScope Pro Agilent Trace Core 2 (ATC2)
- ChipScope Integrated Logic Analyzer (ILA)
- ChipScope Pro IBERT for Virtex-7 GTX
- ChipScope Pro IBERT for 7 Series GTH
- ChipScope Pro (IBERT) for Virtex-6 GTH
- ChipScope Pro IBERT for Virtex-6 FPGA GTX Transceivers
- ChipScope Pro IBERT for Virtex-5 FPGA GTX Transceivers
- ChipScope Pro IBERT for Spartan-6 GTP Transceivers
- Spartan-6 FPGA Embedded Kit
- Virtex-6 FPGA Embedded Kit