ChipScope Pro IBERT for Virtex-6 FPGA GTX Transceivers

Documentation

• Xilinx End User License Agreement

Device Family Support

• Virtex-6

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Radio Tester (IBERT) core for Virtex®-6 FPGA GTX transceivers can be used to evaluate and monitor GTX transceivers. The design includes pattern generators and checkers implemented in FPGA logic, and access to the ports and dynamic reconfiguration port (DRP) attributes of the GTX transceivers. Communication logic is also included to allow the design to be run-time accessible through JTAG. The IBERT core is a self-contained design. When generated, it will run through the entire implementation flow, including bit stream generation.

Key Features

• Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core
• Contains a user-selectable number of Virtex-6 GTX Transceivers
• Transceiver can be customized for the desired line rate, reference clock rate, reference clock source, and data path width
• Requires a system clock that can be sourced from a pin or one of the enabled GTX transceivers