PowerPC Device Control Register Bus
The Xilinx 32-Bit Device Control Register Bus (DCR), a soft IP core designed for Xilinx FPGAs, provides the DCR bus structure as described in the IBM 32-Bit Device Control Register Bus (DCR) Architecture Specification to allow easy connection of the DCR Master to the DCR slaves. It provides the daisy-chain for the DCR data bus and the OR gate for the DCR acknowledge signals from the DCR slaves.
Key Features & Benefits
- DCR connections for one DCR master and a variable number of DCR slaves, which are configurable via design parameter
- Daisy-chain connections for the DCR data bus
- Required OR function of the DCR slaves’ acknowledge signalChange to Show tab