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3GPP LTE Turbo Encoder IP Core Evaluation

Xilinx supports Full System Hardware Evaluation. The evaluation license key for this core will enable you to parameterize, generate and instantiate this IP in your design. It will also allow you to perform functional and timing simulation, generate a bitstream, and download and configure your design in hardware. The resulting IP will be fully functional in the FPGA for certain period of time, after which it will cease to function. To restore the evaluation core's operation in your design, simply reconfigure the FPGA with the bitstream.

Requirements

Please refer to the Requirements link on the product page for this core for information on Software Requirements.

License Terms

Please note that the terms of the Core Evaluation License Agreement apply toward your evaluation of this core. 

Accessing Evaluation Files

To perform a Full System Hardware Evaluation:

  1. Make sure you have satisfied the Software Requirements for this core.
  2. Generate a Full System Hardware Evaluation License Key (see Quick Links box).
    • The license will be generated and emailed to you automatically. Install the license as directed by the email instructions.
  3. Follow the general instructions below to load the IP Catalog customization GUI for this core and generate the core.
  4. For some cores, an Example Design is written to your project directory by the IP Catalog when you generate the core. If an example design is provided, instructions will be documented in a Product Guide document.
  5. To perform an in-depth evaluation in hardware in your own design:
    • Instantiate the core in your own design, place and route the design using Vivado, then generate a bitstream and use it to program an appropriate FPGA device.
    Note: The evaluation core will cease to function in a programmed FPGA device after a period of time.

General Instructions

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

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