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Digital Pre-Distortion (DPD)

Product Description

Xilinx provides a market leading DPD solution that reduces CapEx and OpEx

Digital Pre-Distortion (DPD) is one of the most fundamental building blocks in wireless communication systems today. It is used to increase the efficiency of Power Amplifiers. By reducing the distortion created by running Power Amplifiers in their non-linear regions, Power Amplifiers can be made to be far more efficient. Wireless base stations not employing CFR or DPD algorithms typically exhibit low efficiency, and therefore high operational and capital equipment costs. A typical Class AB LDMOS Power Amplifier with WCDMA waveforms may have approximately 8-15% efficiency. With CFR and DPD turned on, this efficiency can grow to as much as 30-40%, resulting in tremendous savings in CapEx and OpEx for network operators. With later generations of Power Amplifier design leveraging Doherty architectures, efficiencies in the 40%+ range with Xilinx DPD are possible.

The Xilinx DPD core reduces implementation time by providing a high performance DPD solution to customers as a parameterizable core rather than one that needs to be customized by hand. Furthermore, Xilinx DPD is tuned for implementation in Xilinx FPGAs, resulting in a very small FPGA footprint and the lowest cost FPGA solution available today.

Xilinx DPD v7.0 supports the following air interface standards:

  • LTE FDD/TDD
  • LTE/LTE-Advanced
  • TD-SCDMA
  • WCDMA
  • WiMAX
  • CDMA2000
  • MC-GSM

 

Key Features & Benefits

Feature DPD v6.0 DPD v7.0
Typical correction performance 25-35dB 35-40dB
Maximum iBW 100MHz 100MHz
Supported Tx Antennas 1, 2, 4 or 8 1, 2
Supported Clocks and Phases per output sample {Clocks Per Sample}[Phase]
{1, 2, 3, 4}[1], 1 [2]
{1} [1], {1} [2]
491 MHz Clock Support No Yes (With two-phase interface and one phase internal datapath)
Max Sampling Rate 500 MSps 750 MSps
Feedback path 1Fs, 2Fs Real or Complex IF 1Fs, 2Fs Real or Complex IF
Support for Export Compliant ADC Yes Yes
Variable memory matrix parameterization to allow narrow band vs broad band area trade off Yes, 6 Yes, only runtime
Supports processor hardware acceleration to reduce coefficient update times Yes, 3 Yes
Typical update time for 1 antenna, with hardware acceleration <200ms <100ms
QMC Yes Rx
Supported Devices Virtex-6, 7 Series (MicroBlaze) Zynq (ARM)

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

Product Vendor:

Xilinx
xilinx-131x43
Order Evaluate

Part Number:

EF-DI-DPD-SITE

License:

Core License Agreement

Featured Documents