The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channels between transmit and receive cores. This core is not intended to be used standalone and should only be used only in conjunction with the JESD204 core.
Note: This core is provided as standalone IP for use in the JESD204 IP example design only.
Key Features and Benefits
- Designed to JEDEC® JESD204B
- Supports 1 t0 12 lane configurations
- Supports Subclass 0, 1, and 2
- Physical layer functions provided
- Supports trasceiver sharing between TX and RX cores