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JESD204

Product Description

The LogiCORE™ IP JESD204 core is designed to Joint Electron Devices Engineering Council (JEDEC) JESD204B standard.  The JESD204B specification describes serial data interface and the link protocol between data converters and logic devices.

This IP core supports line rates of up to 12.5Gbps on 1, 2, 3, 4, 5, 6, 7, or 8 lanes. The IP Core can be configured as JESD204 Transmitter for interfacing to DAC device or JESD204 Receiver for interfacing to ADC device. The JESD204 IP core is delivered as a netlist along with the supporting wrapper files.

Key Features & Benefits

  • Designed to JEDEC JESD204B specification
  • Supports scrambling and initial lane alignment
  • Supports 1-256 Octets per frame and 1-32 frames per multi-frame
  • Provides Physical and Data link layer functions
  • AXI4-Stream interface for data
  • AXI4-Lite for configuration interface

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

Product Vendor:

Xilinx
xilinx-131x43
Order Evaluate

Part Number:

EF-DI-JESD204-SITE

License:

Core License Agreement

Featured Documents