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USXGMII Subsystem

Product Description

The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with a mechanism to carry a single port of 10M, 100M, 1G, 2.5G, 5G or 10GE over an IEEE 802.3 Clause 49 BASE-R physical coding sublayer/physical layer (PCS/PHY). The USXGMII IP core is delivered as encrypted register transfer level (RTL) through the Vivado® Design Suite targeted for Xilinx UltraScale+ and UltraScale devices.

Key Features & Benefits

  • Designed to meet the USXGMII specification EDCS-1467841 revision 1.4
  • Supports 10M, 100M, 1G, 2.5G, 5G, or 10GE data rates over a 10.3125 Gb/s link
  • Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included
  • Code replication/removal of lower rates onto the 10GE link
  • Rate adaption onto user clock domain
  • 32-bit AXI4-Stream interface for datapath
  • Optional AXI4-Lite register interface
  • Support for 802.3x and priority-based pause operation
  • Detailed statistics gathering
  • Support for custom preambles

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Tools and Device Support

Device Family Support:

Design Tools Support:

Related Products

xilinx-131x43
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  • Part Number:
    EF-DI-USXGMII-MAC-SITE
  • License: Core License Agreement

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