Xilinx provides a generic forward error correction (FEC) engine to generate and insert a SMPTE ST2022 compliant video over IP FEC stream along with the media stream and supporting up to 512 video channels, accelerating time to market and driving the convergence of broadcast and IP networks.
The Video over IP FEC LogiCORE IP enables forward error correction data to be added to IP-based video streams to provide robust broadcast contribution and distribution links. On the transmit side, media payloads from multiple packetized and multiplexed streams enter the Video over IP FEC transmitter. SMPTE ST 2022-1 or ST 2022-5 compliant two-dimensional FEC packets are generated and inserted along with the Media Packet streams. The transmitter also adds the relevant packet header information when needed, for instance in ST 2022 transport protocol, the ST 2022-2 or ST 2022-6 header is added on top of the media payload. Otherwise, the payload can also be sent as-is in a pass-through mode. Media and FEC packets from the Video over IP FEC transmitter need to go through a header insertion module to build complete Ethernet packets before sending out to the MAC. On the receive side, Ethernet packets from the MAC need to go through a de-framer module to remove the lower layer protocol headers before the data stream enters the Video over IP FEC receiver and any lost packets are recovered through the FEC matrix.
Based on standard AXI4-Stream, AXI4-Lite and AXI4-MM interfaces, the FEC engine can easily be integrated into your video over IP system design.
Key Features and Benefits
- SMPTE ST 2022-1 and ST 2022-5 based FEC encoding and recovery
- Up to 512 channels for ST 2022-1 FEC, up to 8 channels for ST 2022-5 FEC
- FEC matrix selection per channel (selectable L & D parameters)
This IP Core has been discontinued. Effective Date: 5/24/2017
Not recommended for new designs. The core is removed from IP catalog as of 2017.2. Please contact Macnica Technology, our IP partner, for available alternative IP.
- FEC interleaving selection per channel (block and non-block aligned)
- FEC operating mode configurable per channel (packet bypass, 1D FEC, 2D FEC)
- FEC recovery on/off per channel