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Fast Fourier Transform (FFT)

Product Description

The Fast Fourier Transform (FFT) is a fundamental building block used in DSP systems, with applications ranging from OFDM based Digital MODEMs, to Ultrasound, RADAR and CT Image reconstruction algorithms. Although its algorithm is quite easily understood, the variants of the implementation architectures and specifics are significant and are a large time sink for hardware engineers today.

The FFT LogiCORE™ IP core provides four different architectures along with system level fixed point C-models, and reduces typical implementation time from between 3-6 months to the push of a button. It also provides users with the ability to make all the necessary algorithmic and implementation specific trade-offs demanded by both DSP algorithm and hardware engineers. These easily made trade-offs give users the ability to select the most resource and power efficient solutions for the specific point size and transform time needed for their application.

FFT LogiCORE expands the focus on increased dynamic range by increasing data and phase factor width support up to 34 bits and supporting IEEE single precision floating point data type. The floating point option is implemented by utilizing a higher precision fixed-point FFT internally to achieve similar noise performance to a full floating point implementation, with significantly fewer resources.

Key Features & Benefits

  • AXI4-Stream compliant interfaces.
  • Forward and inverse complex FFT, run time configurable
  • Transform sizes n = 2m, m = 3 - 16
  • Data sample precision bx = 8 - 34
  • Phase factor precision bx = 8 - 34
  • Arithmetic types:
    • Unscaled (full-precision) fixed-point
    • Scaled fixed-point
    • Block floating-point
  • Fixed-point or floating-point interface
  • Rounding or truncation after the butterfly
  • Block RAM of Distributed RAM for data and phase-factor storage
  • Optional run time configurable transform point size
  • Run time configurable scaling schedule for scaled fixed-point cores
  • Bit/digit reversed or natural output order
  • Optional cyclic prefix insertion for digital communications systems
  • Four architectures offer a trade-off between core size and transform time
  • Bit accurate C model and MEX function for system modeling available for download

 

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  • Bundled With: Vivado Design Suite
    ISE Design Suite
  • License: Xilinx End User License Agreement
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