Allegro FPGA System Planner

Device Family Support

• Artix-7
• Kintex-7
• Spartan-3
• Spartan-3A
• Spartan-6 LX
• Virtex-4
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Virtex-5
• Virtex-5 LX
• Virtex-6 LXT
• Virtex-7
• Zynq

The Cadence® Allegro® FPGA System Planner offers a complete, scalable technology for FPGA-PCB co-design that allows users to create an optimum correct-by-construction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectivity, FPGA device pin assignment rules, and placement of FPGAs on the PCB. With automatic pin assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB. This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches while shortening the design cycle time.

Key Features

• Accelerates integration of FPGAs with Cadence PCB design creation environments
• Allows architectural exploration for FPGA system
• Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors
• Eliminates unnecessary, frustrating design iterations during the PCB layout process
• Enables interface-based connectivity definition for the FPGA system
• Enables placement-aware pin assignment synthesis that is FPGA-DRC accurate
• Reduces PCB layer count through placement-aware pin assignment and optimization
• Scalable FPGA-PCB co-design solution from OrCAD Capture to Allegro GXL
• Shortens time for optimum initial pin assignment, accelerating PCB design schedules
• Speeds ASIC prototyping using FPGAs

Target Markets

• Broadcast
• Automotive
• High Performance Computing
• Consumer
• Aerospace & Defense
• Industrial Scientific Medical
• Industrial Scientific Medical
• Wired Communications
• Wireless Communications