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Instruction-Side On-Chip Memory (ISOCM) BRAM Interface Controller

Product Description

The ISOCM BRAM Interface Controller connects a BRAM block to the Instruction-Side On-Chip Memory (DSOCM) bus in PowerPC 405 based embedded systems.

Key Features & Benefits

  • Used with BRAM block peripheral to provide a deterministic ISBRAM memory solution for PowerPC 405.
  • Utilizes dual port features of BRAM.
  • Debug access via DCR.
  • Configurable permanent BRAM enable for improved performance.

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Tools and Device Support

Device Family Support:

Design Tools Support:

  • Bundled With: Embedded Development Kit
  • License: Xilinx End User License Agreement

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