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JTAG to AXI Master

Product Description

The LogiCORE™ JTAG to AXI Master IP core is a customizable core that can generate the AXI transactions and drive the AXI signals internal to FPGA in the system. This supports AXI4 interfaces and Lite protocol and can be selected using a parameter. The width of AXI data bus is customizable. This IP can drive AXI4-Lite or AXI4 Memory mapped Slave through an AXI4 interconnect. This can also be connected to interconnect as master. Run time interaction with this core requires the use of the Vivado® logic analyzer feature.

Key Features & Benefits

  • Provides AXI4 master interface
  • Option to set AXI4 and AXI4-Lite interfaces
  • User Selectable AXI datawidth – 32 and 64
  • User Selectable AXI ID width up to four bits
  • Vivado logic analyzer Tcl Console interface to interact with hardware
  • Support  AXI4 and Lite transactions
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  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement

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