HDL Coder™ generates portable, synthesizable VHDL® and Verilog® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design. HDL Coder provides a workflow advisor that automates the programming of Xilinx® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated HDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
Key Features
- Code generation support for MATLAB functions, System objects, and Simulink blocks
- Code-to-model and model-to-code traceability for DO-254
- Legacy code integration
- Mealy and Moore finite-state machines and control logic implementations using Stateflow
- Resource sharing and retiming for area-speed tradeoffs
- Target-independent, synthesizable VHDL and Verilog code
- Workflow advisor for programming Xilinx application boards
Target Markets
- Automotive
- High Performance Computing
- Consumer
- Aerospace & Defense
- Industrial Scientific Medical
- Industrial Scientific Medical
- Wired Communications
- Wireless Communications
- Broadcast