Xilinx End User License
The multiplier operation is essential and abundant in DSP Applications. Achieving maximum implementation efficiency and clock performance is therefore critical to DSP systems and frequently presents a significant challenge to hardware engineers.
The Multiplier LogiCORE™ simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. The multiplier is able to generate parallel multipliers, and constant coefficient multipliers, both with differing implementation styles. Furthermore, with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system.
The latest additions to the IP provide fine control over the latency (pipelining) of the multipliers (purely combinatorial to fully pipelined) and symmetric rounding on XtremeDSPTM slice based multiplication under 18 bits. Finally, fully pipelined implementations enable maximum clock frequency performance of 450 MHz and 250 MHz when DSP48 components are used in Virtex™-6 (-1) and Spartan™-6 (-2) respectively.
New Features in v11.2