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PLBV46 to AXI Bridge

Product Description

The Processor Local Bus (PLB v4.6) to AMBA® (Advanced Microcontroller Bus Architecture) Advanced eXtensible Interface (AXI) Bridge translates PLBV46 transactions into AXI4 transactions. It functions as a slave on the PLBV46 and as a master on the AXI4. The PLBV46 to AXI Bridge main use model is to connect the AXI slaves with PLB masters.

Key Features & Benefits

  • Connects as a 32/64-bit slave on PLB v4.6 buses of 32, 64 or 128 bits
  • Supports 1:1 (PLB:AXI) synchronous clock ratio
  • Supports access by 32, 64-bit PLB masters
  • Single transfers of 1 to 8 bytes
  • Optional line transfers of 4 and 8 words
  • Optional Fixed length burst transfers of 2 to 16 data beats of words and double words
  • Supports optional two levels of address pipelining
  • Supports split bus architecture (simultaneous read and write operations)
  • Supports optional PLB status/interrupt registers and generates interrupts
xilinx-131x43
  • Bundled With: Embedded Development Kit
    Vivado Design Suite
  • License: Xilinx End User License Agreement

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