PLBV46 to DCR
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- ISE Design Suite
Documentation
Device Family Support
- Virtex-5 FX
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SX
- Virtex-5 SXT
- Virtex-5 TXT
- Virtex-4
The PLBV46 to DCR Bridge translates transactions received on its PLB interface into DCR master operations.Its design utilizes an PLB interface module to abstract PLB transactions into a simple SRAM style protocol that is easier to design with.
Key Features
- Connects as a 32-bit slave on PLB V4.6 buses of 32-bit, 64-bit, or 128-bit
- 32-bit DCR master data width with a 10-bit DCR address bus
- Memory-mapped interface from PLB to DCR, no special instructions required
- Increased timing flexibility in typical systems where the PLB clock is slower than the CPU clock